Emacs is my preferred tool for development, statistical computing, and writing. The killer feature is without doubt https://orgmode.org/ which allows for powerful literate programming, handling of bibliographies, organizing notes collections, and much more.

I finally decided to make the move from my vanilla emacs configuration to Doom Emacs. This gives an optimized emacs experience with fast load times due to lazy-loading of packages, and more importantly, the maintainer is doing an amazing job on adapting to new features and changes to emacs and the various lisp packages. A task which I found increasingly time-consuming.

In a recent paper: A two-stage estimation procedure for non-linear structural equation models by Klaus Kähler Holst & Esben Budtz-Jørgensen (https://doi.org/10.1093/biostatistics/kxy082), we consider two-stage estimators as a computationally simple alternative to MLE. Here both steps are based on linear models: first we predict the non-linear terms and then these are related to latent outcomes in the second step.

Logic gates are the building blocks of digital electronics. Simple logic gates are efficiently implemented in various IC packages such as the 74HCXX series. However, it is educational to have a look at the implementation using just NPN transistors.

A small illustration on using the armadillo C++ linear algebra library for solving an ordinary differential equation of the form $$X^{\prime }(t)=F(t,X(t),U(t)).$$

The abstract super class Solver defines the methods solve (for approximating the solution in user-defined time-points) and solveint (for interpolating user-defined input functions on finer grid). As an illustration a simple Runge-Kutta solver is derived in the class RK4.

The first step is to define the ODE, here a simple one-dimensional ODE $X^{\prime }(t)=\theta \cdot \{U(t)-X(t)\}$ with a single input $U(t)$:

rowvec dX(const rowvec &input, // time (first element) and additional input variables
	 const rowvec &x,     // state variables
	 const rowvec &theta) {   // parameters
  rowvec res = { theta(0)*theta(1)*(input(1)-x(0)) };
  return( res );
}

The ODE may then be solved using the following syntax

odesolver::RK4 MyODE(dX);
arma::mat res = MyODE.solve(input, init, theta);

with the step size defined implicitly by input (first column is the time variable and the following columns the optional different input variables) and boundary conditions defined by init.

The 74HC595: an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

If higher load is required there is also the TPIC6C595 (e.g., for driving LEDs), or it should be paired with for example ULN2803 or similar. For multiple inputs see the 74HC165.

The basic usage is to serially transfer a byte from a microcontroller to the IC. When latched the byte will then in parallel be available on output pins QA-QH (Q0-Q7).

$$ Relative risks (and risk differences) are collapsible and generally considered easier to interpret than odds-ratios. In a recent publication Richardson et al (JASA, 2017) proposed a new regression model for a binary exposure which solves the computational problems that are associated with using for example binomial regression with a log-link function (or identify link for the risk difference) to obtain such parameter estimates.

Let $Y$ be the binary response, $A$ binary exposure, and $V$ a vector of covariates, then the target parameter is

$$\begin{array}{rl}& \mathrm{RR}(v)=\frac{\mathbb{P}(Y=1\mid A=1,V=v)}{\mathbb{P}(Y=1\mid A=0,V=v)}.\end{array}$$

Let $p_a(V)=\mathbb{P}(Y\mid A=a,V),a\in \{0,1\}$, the idea is then to posit a linear model for $$\theta (v)=\log (RR(v))$$ and a nuisance model for the odds-product $$\varphi (v)=\log \left(\frac{p_0(v)p_1(v)}{(1-p_0(v))(1-p_1(v))}\right)$$ noting that these two parameters are variation independent which can be from the below L’Abbé plot. Similarly, a model can be constructed for the risk-difference on the following scale $$\theta (v)=\mathrm{arctanh}(RD(v)).$$

The 74HC165 is an 8-bit parallel-load or serial-in shift register.

Wiring:

• Pin 8 (GND): GND
• Pin 16 (VCC): Voltage 5V
• Pin 11-14 & 3-6 (A-H): Input 1-8
• Pin 1 (SH/LD): shift/load pin
• Pin 2 (CLK): Clock pin
• Pin 9 (QH): Data output pin
• Pin 15 (CLK INH): Clock-inhibit pin (or GND)

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. CLK INH can be wired to GND to save a pin on the microcontroller. Unused inputs pins should be grounded as well.

Multiple 74HC165 ICs can be daisy chained by wiring the serial-out pin 9 (QH) to pin 10 (SER) of the succeeding IC allowing us to tie multiple 74165 ICs together that can be controlled using only 3 pins.